A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints

A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The metho...

وصف كامل

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Harmanani, Haidar M. (author)
مؤلفون آخرون:	Salamy, Hassan A. (author)
التنسيق:	article
منشور في:	2006
الوصول للمادة أونلاين:	http://hdl.handle.net/10725/3534 http://dx.doi.org/10.1142/S1469026806002052 http://www.worldscientific.com/doi/abs/10.1142/S1469026806002052
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