Harmanani, H. M., & Sawan, R. (2017). Test time minimization for system-on-chip with test bus assignment and sizin.
Chicago Style (17th ed.) CitationHarmanani, Haidar M., and Rachel Sawan. Test Time Minimization for System-on-chip with Test Bus Assignment and Sizin. 2017.
MLA (9th ed.) CitationHarmanani, Haidar M., and Rachel Sawan. Test Time Minimization for System-on-chip with Test Bus Assignment and Sizin. 2017.
Warning: These citations may not always be 100% accurate.