Test time minimization for system-on-chip with test bus assignment and sizin
Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | |
| التنسيق: | conferenceObject |
| منشور في: |
2017
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5457 http://dx.doi.org/10.1109/NEWCAS.2007.4488014 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4488014/ |
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| _version_ | 1864513477058494464 |
|---|---|
| author | Harmanani, Haidar M. |
| author2 | Sawan, Rachel |
| author2_role | author |
| author_facet | Harmanani, Haidar M. Sawan, Rachel |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, Haidar M. Sawan, Rachel |
| dc.date.none.fl_str_mv | 2017-03-29T11:25:58Z 2017-03-29T11:25:58Z 2017-03-29 |
| dc.identifier.none.fl_str_mv | 978-1-4244-1163-4 http://hdl.handle.net/10725/5457 http://dx.doi.org/10.1109/NEWCAS.2007.4488014 Harmanani, H. M., & Sawan, R. (2007, August). Test time minimization for system-on-chip with test bus assignment and sizing. In Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on (pp. 1281-1284). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4488014/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Test time minimization for system-on-chip with test bus assignment and sizin |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_93f700d9ff7a487bfb87bfc11053a0da |
| identifier_str_mv | 978-1-4244-1163-4 Harmanani, H. M., & Sawan, R. (2007, August). Test time minimization for system-on-chip with test bus assignment and sizing. In Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on (pp. 1281-1284). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5457 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Test time minimization for system-on-chip with test bus assignment and sizinHarmanani, Haidar M.Sawan, RachelTest access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method.N/AIEEE2017-03-29T11:25:58Z2017-03-29T11:25:58Z2017-03-29Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject978-1-4244-1163-4http://hdl.handle.net/10725/5457http://dx.doi.org/10.1109/NEWCAS.2007.4488014Harmanani, H. M., & Sawan, R. (2007, August). Test time minimization for system-on-chip with test bus assignment and sizing. In Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on (pp. 1281-1284). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/4488014/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54572021-03-19T10:00:56Z |
| spellingShingle | Test time minimization for system-on-chip with test bus assignment and sizin Harmanani, Haidar M. |
| status_str | publishedVersion |
| title | Test time minimization for system-on-chip with test bus assignment and sizin |
| title_full | Test time minimization for system-on-chip with test bus assignment and sizin |
| title_fullStr | Test time minimization for system-on-chip with test bus assignment and sizin |
| title_full_unstemmed | Test time minimization for system-on-chip with test bus assignment and sizin |
| title_short | Test time minimization for system-on-chip with test bus assignment and sizin |
| title_sort | Test time minimization for system-on-chip with test bus assignment and sizin |
| url | http://hdl.handle.net/10725/5457 http://dx.doi.org/10.1109/NEWCAS.2007.4488014 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4488014/ |