Test time minimization for system-on-chip with test bus assignment and sizin
Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration...
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| Format: | conferenceObject |
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2017
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| Online Access: | http://hdl.handle.net/10725/5457 http://dx.doi.org/10.1109/NEWCAS.2007.4488014 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4488014/ |
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