Register binding for FPGAs with embedded memory
The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | |
| التنسيق: | conferenceObject |
| منشور في: |
2017
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5807 http://dx.doi.org/10.1109/FCCM.2004.49 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1364627/ |
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| _version_ | 1864513477867995136 |
|---|---|
| author | Ouaiss, I. |
| author2 | Atat, H.A. |
| author2_role | author |
| author_facet | Ouaiss, I. Atat, H.A. |
| author_role | author |
| dc.creator.none.fl_str_mv | Ouaiss, I. Atat, H.A. |
| dc.date.none.fl_str_mv | 2017-06-21T10:16:44Z 2017-06-21T10:16:44Z 2017-06-21 |
| dc.identifier.none.fl_str_mv | 0-7695-2230-0 http://hdl.handle.net/10725/5807 http://dx.doi.org/10.1109/FCCM.2004.49 Atat, H. A., & Ouaiss, I. (2004, April). Register binding for FPGAs with embedded memory. In Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on (pp. 165-175). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1364627/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Register binding for FPGAs with embedded memory |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits by sharing variables among registers and thus minimizing the required number of registers for a specific design. In this paper, a new technique is proposed that makes use of the existing embedded memory blocks and maps variables to these blocks. The proposed memory binding approach gives considerable performance increase over the existing register binding techniques. The memory binding technique resulted in up to 57% savings in the total chip area (number of logic cells/elements occupied on the FPGA) over the old register binding techniques for a small resource bag and up to 6% savings for a large resource bag. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_979b80fa4b22276f56cbf204bdb8e79d |
| identifier_str_mv | 0-7695-2230-0 Atat, H. A., & Ouaiss, I. (2004, April). Register binding for FPGAs with embedded memory. In Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on (pp. 165-175). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5807 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Register binding for FPGAs with embedded memoryOuaiss, I.Atat, H.A.The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits by sharing variables among registers and thus minimizing the required number of registers for a specific design. In this paper, a new technique is proposed that makes use of the existing embedded memory blocks and maps variables to these blocks. The proposed memory binding approach gives considerable performance increase over the existing register binding techniques. The memory binding technique resulted in up to 57% savings in the total chip area (number of logic cells/elements occupied on the FPGA) over the old register binding techniques for a small resource bag and up to 6% savings for a large resource bag.N/AIEEE2017-06-21T10:16:44Z2017-06-21T10:16:44Z2017-06-21Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject0-7695-2230-0http://hdl.handle.net/10725/5807http://dx.doi.org/10.1109/FCCM.2004.49Atat, H. A., & Ouaiss, I. (2004, April). Register binding for FPGAs with embedded memory. In Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on (pp. 165-175). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/1364627/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/58072021-03-19T10:00:57Z |
| spellingShingle | Register binding for FPGAs with embedded memory Ouaiss, I. |
| status_str | publishedVersion |
| title | Register binding for FPGAs with embedded memory |
| title_full | Register binding for FPGAs with embedded memory |
| title_fullStr | Register binding for FPGAs with embedded memory |
| title_full_unstemmed | Register binding for FPGAs with embedded memory |
| title_short | Register binding for FPGAs with embedded memory |
| title_sort | Register binding for FPGAs with embedded memory |
| url | http://hdl.handle.net/10725/5807 http://dx.doi.org/10.1109/FCCM.2004.49 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1364627/ |