Test insertion at the RT level using functional test metrics
A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | conferenceObject |
| Published: |
2017
|
| Online Access: | http://hdl.handle.net/10725/5464 http://dx.doi.org/10.1006/bbrc.1994.188310.1109/ICECS.2000.913048 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/913048/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1864513465873334272 |
|---|---|
| author | Harmanani, H. |
| author2 | Harfoush, S. |
| author2_role | author |
| author_facet | Harmanani, H. Harfoush, S. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, H. Harfoush, S. |
| dc.date.none.fl_str_mv | 2017-03-30T10:08:11Z 2017-03-30T10:08:11Z 2017-03-30 |
| dc.identifier.none.fl_str_mv | 0-7803-6542-9 http://hdl.handle.net/10725/5464 http://dx.doi.org/10.1006/bbrc.1994.188310.1109/ICECS.2000.913048 Harmanani, H., & Harfoush, S. (2000). Test insertion at the RT level using functional test metrics. In Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on (Vol. 2, pp. 1016-1020). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/913048/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Test insertion at the RT level using functional test metrics |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The system outputs a VHDL description of a testable data path along with a test plan. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_a56a43b8d4bcec22b48c46f0c57199b7 |
| identifier_str_mv | 0-7803-6542-9 Harmanani, H., & Harfoush, S. (2000). Test insertion at the RT level using functional test metrics. In Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on (Vol. 2, pp. 1016-1020). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5464 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Test insertion at the RT level using functional test metricsHarmanani, H.Harfoush, S.A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The system outputs a VHDL description of a testable data path along with a test plan.N/AIEEE2017-03-30T10:08:11Z2017-03-30T10:08:11Z2017-03-30Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject0-7803-6542-9http://hdl.handle.net/10725/5464http://dx.doi.org/10.1006/bbrc.1994.188310.1109/ICECS.2000.913048Harmanani, H., & Harfoush, S. (2000). Test insertion at the RT level using functional test metrics. In Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on (Vol. 2, pp. 1016-1020). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/913048/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54642021-03-19T10:03:24Z |
| spellingShingle | Test insertion at the RT level using functional test metrics Harmanani, H. |
| status_str | publishedVersion |
| title | Test insertion at the RT level using functional test metrics |
| title_full | Test insertion at the RT level using functional test metrics |
| title_fullStr | Test insertion at the RT level using functional test metrics |
| title_full_unstemmed | Test insertion at the RT level using functional test metrics |
| title_short | Test insertion at the RT level using functional test metrics |
| title_sort | Test insertion at the RT level using functional test metrics |
| url | http://hdl.handle.net/10725/5464 http://dx.doi.org/10.1006/bbrc.1994.188310.1109/ICECS.2000.913048 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/913048/ |