An incremental approach for test scheduling and synthesis using genetic algorithms
This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and multiplexers. The method is based on a genetic algorithm that efficiently...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| مؤلفون آخرون: | |
| التنسيق: | conferenceObject |
| منشور في: |
2017
|
| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5442 http://dx.doi.org/10.1109/NEWCAS.2004.1359019 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1359019/ |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
| _version_ | 1864513477033328640 |
|---|---|
| author | Harmanani, H. |
| author2 | Hajar, A. |
| author2_role | author |
| author_facet | Harmanani, H. Hajar, A. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, H. Hajar, A. |
| dc.date.none.fl_str_mv | 2017-03-28T09:43:13Z 2017-03-28T09:43:13Z 2017-03-28 |
| dc.identifier.none.fl_str_mv | 0-7803-8322-2 http://hdl.handle.net/10725/5442 http://dx.doi.org/10.1109/NEWCAS.2004.1359019 Harmanani, H., & Hajar, A. (2004, June). An incremental approach for test scheduling and synthesis using genetic algorithms. In Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on (pp. 69-72). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1359019/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | An incremental approach for test scheduling and synthesis using genetic algorithms |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and multiplexers. The method is based on a genetic algorithm that efficiently explores the testable design space. The method was implemented using C++ on a Linux workstation. Several benchmark examples have been implemented and favorable results are reported. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_accb7cd13ed49ac1c22ee726652dba7f |
| identifier_str_mv | 0-7803-8322-2 Harmanani, H., & Hajar, A. (2004, June). An incremental approach for test scheduling and synthesis using genetic algorithms. In Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on (pp. 69-72). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5442 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | An incremental approach for test scheduling and synthesis using genetic algorithmsHarmanani, H.Hajar, A.This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and multiplexers. The method is based on a genetic algorithm that efficiently explores the testable design space. The method was implemented using C++ on a Linux workstation. Several benchmark examples have been implemented and favorable results are reported.N/AIEEE2017-03-28T09:43:13Z2017-03-28T09:43:13Z2017-03-28Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject0-7803-8322-2http://hdl.handle.net/10725/5442http://dx.doi.org/10.1109/NEWCAS.2004.1359019Harmanani, H., & Hajar, A. (2004, June). An incremental approach for test scheduling and synthesis using genetic algorithms. In Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on (pp. 69-72). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/1359019/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54422021-03-19T10:03:22Z |
| spellingShingle | An incremental approach for test scheduling and synthesis using genetic algorithms Harmanani, H. |
| status_str | publishedVersion |
| title | An incremental approach for test scheduling and synthesis using genetic algorithms |
| title_full | An incremental approach for test scheduling and synthesis using genetic algorithms |
| title_fullStr | An incremental approach for test scheduling and synthesis using genetic algorithms |
| title_full_unstemmed | An incremental approach for test scheduling and synthesis using genetic algorithms |
| title_short | An incremental approach for test scheduling and synthesis using genetic algorithms |
| title_sort | An incremental approach for test scheduling and synthesis using genetic algorithms |
| url | http://hdl.handle.net/10725/5442 http://dx.doi.org/10.1109/NEWCAS.2004.1359019 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1359019/ |