A Novel Register Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis

Optimizing area and timing have long been considered to be the main design challenges in high-level synthesis. A lot of research has been conducted in this area and many techniques to improve performance have been suggested. However, as design applications become more power-sensitive, and with the e...

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Bibliographic Details
Main Author: Ouaiss, Iyad (author)
Other Authors: Elaaraj, Elie (author)
Format: article
Published: 2011
Online Access:http://hdl.handle.net/10725/3170
http://dx.doi.org/10.1142/S0218126611007700
http://www.worldscientific.com/doi/abs/10.1142/S0218126611007700
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