Thermal-aware test scheduling using network-on-chip under multiple clock rates
The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an...
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2013
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| Online Access: | http://hdl.handle.net/10725/3526 http://dx.doi.org/10.1080/00207217.2012.713016 http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.713016 |
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| _version_ | 1864513461372846080 |
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| author | Harmanani, Haidar M. |
| author2 | Salamy, Hassan |
| author2_role | author |
| author_facet | Harmanani, Haidar M. Salamy, Hassan |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, Haidar M. Salamy, Hassan |
| dc.date.none.fl_str_mv | 2013 2016-04-11T11:47:24Z 2016-04-11T11:47:24Z 2017-07-27 |
| dc.identifier.none.fl_str_mv | 0020-7217 http://hdl.handle.net/10725/3526 http://dx.doi.org/10.1080/00207217.2012.713016 Salamy, H., & Harmanani, H. M. (2013). Thermal-aware test scheduling using network-on-chip under multiple clock rates. International Journal of Electronics, 100(3), 408-424. http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.713016 |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | International Journal of Electronics |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| dc.type.none.fl_str_mv | Article info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | LAURepo_cd358955e11070e826c8194a35c5e6f2 |
| identifier_str_mv | 0020-7217 Salamy, H., & Harmanani, H. M. (2013). Thermal-aware test scheduling using network-on-chip under multiple clock rates. International Journal of Electronics, 100(3), 408-424. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/3526 |
| publishDate | 2013 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Thermal-aware test scheduling using network-on-chip under multiple clock ratesHarmanani, Haidar M.Salamy, HassanThe increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.PublishedN/A2016-04-11T11:47:24Z2016-04-11T11:47:24Z20132017-07-27Articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article0020-7217http://hdl.handle.net/10725/3526http://dx.doi.org/10.1080/00207217.2012.713016Salamy, H., & Harmanani, H. M. (2013). Thermal-aware test scheduling using network-on-chip under multiple clock rates. International Journal of Electronics, 100(3), 408-424.http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.713016enInternational Journal of Electronicsinfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/35262021-03-19T10:00:46Z |
| spellingShingle | Thermal-aware test scheduling using network-on-chip under multiple clock rates Harmanani, Haidar M. |
| status_str | publishedVersion |
| title | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| title_full | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| title_fullStr | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| title_full_unstemmed | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| title_short | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| title_sort | Thermal-aware test scheduling using network-on-chip under multiple clock rates |
| url | http://hdl.handle.net/10725/3526 http://dx.doi.org/10.1080/00207217.2012.713016 http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.713016 |