Power-constrained system-on-a-chip test scheduling using a genetic algorithm
This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless&quo...
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| Format: | article |
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2006
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| Online Access: | http://hdl.handle.net/10725/3529 http://dx.doi.org/10.1142/S0218126606003106 http://www.worldscientific.com/doi/abs/10.1142/S0218126606003106 |
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| _version_ | 1864513461375991808 |
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| author | Harmanani, Haidar M. |
| author2 | Salamy, Hassan A. |
| author2_role | author |
| author_facet | Harmanani, Haidar M. Salamy, Hassan A. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, Haidar M. Salamy, Hassan A. |
| dc.date.none.fl_str_mv | 2006 2016-04-11T12:47:00Z 2016-04-11T12:47:00Z 2017-04-07 |
| dc.identifier.none.fl_str_mv | 0218-1266 http://hdl.handle.net/10725/3529 http://dx.doi.org/10.1142/S0218126606003106 Harmanani, H. M., & Salamy, H. A. (2006). Power-constrained system-on-a-chip test scheduling using a genetic algorithm. Journal of Circuits, Systems, and Computers, 15(03), 331-349. http://www.worldscientific.com/doi/abs/10.1142/S0218126606003106 |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | Journal of Circuits, Systems and Computers |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| dc.type.none.fl_str_mv | Article info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. The method achieved optimal test schedules in all attempted cases in a short CPU time. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | LAURepo_fccf8b14f06a01e2a298a0fa6a74adf1 |
| identifier_str_mv | 0218-1266 Harmanani, H. M., & Salamy, H. A. (2006). Power-constrained system-on-a-chip test scheduling using a genetic algorithm. Journal of Circuits, Systems, and Computers, 15(03), 331-349. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/3529 |
| publishDate | 2006 |
| repository.mail.fl_str_mv | |
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| spelling | Power-constrained system-on-a-chip test scheduling using a genetic algorithmHarmanani, Haidar M.Salamy, Hassan A.This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. The method achieved optimal test schedules in all attempted cases in a short CPU time.PublishedN/A2016-04-11T12:47:00Z2016-04-11T12:47:00Z20062017-04-07Articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article0218-1266http://hdl.handle.net/10725/3529http://dx.doi.org/10.1142/S0218126606003106Harmanani, H. M., & Salamy, H. A. (2006). Power-constrained system-on-a-chip test scheduling using a genetic algorithm. Journal of Circuits, Systems, and Computers, 15(03), 331-349.http://www.worldscientific.com/doi/abs/10.1142/S0218126606003106enJournal of Circuits, Systems and Computersinfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/35292021-03-19T10:00:46Z |
| spellingShingle | Power-constrained system-on-a-chip test scheduling using a genetic algorithm Harmanani, Haidar M. |
| status_str | publishedVersion |
| title | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| title_full | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| title_fullStr | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| title_full_unstemmed | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| title_short | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| title_sort | Power-constrained system-on-a-chip test scheduling using a genetic algorithm |
| url | http://hdl.handle.net/10725/3529 http://dx.doi.org/10.1142/S0218126606003106 http://www.worldscientific.com/doi/abs/10.1142/S0218126606003106 |