A genetic algorithm for testable data path synthesis
A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and solved using an efficient genetic algorithm that generates cost-effective testabl...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | conferenceObject |
| منشور في: |
2017
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5462 http://dx.doi.org/10.1109/CCECE.2001.933689 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/933689/ |
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| _version_ | 1864513477066883072 |
|---|---|
| author | Harmanani, H. |
| author2 | Saliba, R. Khoury, M. |
| author2_role | author author |
| author_facet | Harmanani, H. Saliba, R. Khoury, M. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, H. Saliba, R. Khoury, M. |
| dc.date.none.fl_str_mv | 2017-03-30T09:14:50Z 2017-03-30T09:14:50Z 2017-03-30 |
| dc.identifier.none.fl_str_mv | 0-7803-6715-4 http://hdl.handle.net/10725/5462 http://dx.doi.org/10.1109/CCECE.2001.933689 Harmanani, H., Saliba, R., & Khoury, M. (2001). A genetic algorithm for testable data path synthesis. In Electrical and Computer Engineering, 2001. Canadian Conference on (Vol. 1, pp. 235-240). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/933689/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | A genetic algorithm for testable data path synthesis |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and solved using an efficient genetic algorithm that generates cost-effective testable designs. We follow the allocation method with an automatic test point selection algorithm that trades off design area and delay with test quality. The method is implemented and design comparisons are reported. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_fd0f64a45f1e93fb861fafbb821648b5 |
| identifier_str_mv | 0-7803-6715-4 Harmanani, H., Saliba, R., & Khoury, M. (2001). A genetic algorithm for testable data path synthesis. In Electrical and Computer Engineering, 2001. Canadian Conference on (Vol. 1, pp. 235-240). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5462 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A genetic algorithm for testable data path synthesisHarmanani, H.Saliba, R.Khoury, M.A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and solved using an efficient genetic algorithm that generates cost-effective testable designs. We follow the allocation method with an automatic test point selection algorithm that trades off design area and delay with test quality. The method is implemented and design comparisons are reported.N/AIEEE2017-03-30T09:14:50Z2017-03-30T09:14:50Z2017-03-30Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject0-7803-6715-4http://hdl.handle.net/10725/5462http://dx.doi.org/10.1109/CCECE.2001.933689Harmanani, H., Saliba, R., & Khoury, M. (2001). A genetic algorithm for testable data path synthesis. In Electrical and Computer Engineering, 2001. Canadian Conference on (Vol. 1, pp. 235-240). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/933689/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54622021-03-19T10:03:24Z |
| spellingShingle | A genetic algorithm for testable data path synthesis Harmanani, H. |
| status_str | publishedVersion |
| title | A genetic algorithm for testable data path synthesis |
| title_full | A genetic algorithm for testable data path synthesis |
| title_fullStr | A genetic algorithm for testable data path synthesis |
| title_full_unstemmed | A genetic algorithm for testable data path synthesis |
| title_short | A genetic algorithm for testable data path synthesis |
| title_sort | A genetic algorithm for testable data path synthesis |
| url | http://hdl.handle.net/10725/5462 http://dx.doi.org/10.1109/CCECE.2001.933689 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/933689/ |