Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
<p>Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | , |
| Published: |
2021
|
| Subjects: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1864513560360517632 |
|---|---|
| author | Jihad Mohamed Aljaam (16864257) |
| author2 | Ramzi A. Jaber (16888755) Somaya Ali Al-Maadeed (16864254) |
| author2_role | author author |
| author_facet | Jihad Mohamed Aljaam (16864257) Ramzi A. Jaber (16888755) Somaya Ali Al-Maadeed (16864254) |
| author_role | author |
| dc.creator.none.fl_str_mv | Jihad Mohamed Aljaam (16864257) Ramzi A. Jaber (16888755) Somaya Ali Al-Maadeed (16864254) |
| dc.date.none.fl_str_mv | 2021-04-12T00:00:00Z |
| dc.identifier.none.fl_str_mv | 10.1109/access.2021.3072567 |
| dc.relation.none.fl_str_mv | https://figshare.com/articles/journal_contribution/Novel_Ternary_Adder_and_Multiplier_Designs_Without_Using_Decoders_or_Encoders/24042504 |
| dc.rights.none.fl_str_mv | CC BY 4.0 info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Engineering Electronics, sensors and digital hardware Information and computing sciences Distributed computing and systems software Mathematical sciences Applied mathematics Transistors CNTFETs Logic gates Power supplies Threshold voltage Internet of Things Energy consumption Carbon nano-tube field effect transistors (CNTFET) Noise immunity curve (NIC) PVT variations Ternary logic circuits Unary operators |
| dc.title.none.fl_str_mv | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| dc.type.none.fl_str_mv | Text Journal contribution info:eu-repo/semantics/publishedVersion text contribution to journal |
| description | <p>Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.</p><h2>Other Information</h2><p>Published in: IEEE Access<br>License: <a href="https://creativecommons.org/licenses/by/4.0/legalcode" target="_blank">https://creativecommons.org/licenses/by/4.0/</a><br>See article on publisher's website: <a href="https://dx.doi.org/10.1109/access.2021.3072567" target="_blank">https://dx.doi.org/10.1109/access.2021.3072567</a></p> |
| eu_rights_str_mv | openAccess |
| id | Manara2_358131e3d3bd6a1494ce3ade14fc01b7 |
| identifier_str_mv | 10.1109/access.2021.3072567 |
| network_acronym_str | Manara2 |
| network_name_str | Manara2 |
| oai_identifier_str | oai:figshare.com:article/24042504 |
| publishDate | 2021 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| rights_invalid_str_mv | CC BY 4.0 |
| spelling | Novel Ternary Adder and Multiplier Designs Without Using Decoders or EncodersJihad Mohamed Aljaam (16864257)Ramzi A. Jaber (16888755)Somaya Ali Al-Maadeed (16864254)EngineeringElectronics, sensors and digital hardwareInformation and computing sciencesDistributed computing and systems softwareMathematical sciencesApplied mathematicsTransistorsCNTFETsLogic gatesPower suppliesThreshold voltageInternet of ThingsEnergy consumptionCarbon nano-tube field effect transistors (CNTFET)Noise immunity curve (NIC)PVT variationsTernary logic circuitsUnary operators<p>Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.</p><h2>Other Information</h2><p>Published in: IEEE Access<br>License: <a href="https://creativecommons.org/licenses/by/4.0/legalcode" target="_blank">https://creativecommons.org/licenses/by/4.0/</a><br>See article on publisher's website: <a href="https://dx.doi.org/10.1109/access.2021.3072567" target="_blank">https://dx.doi.org/10.1109/access.2021.3072567</a></p>2021-04-12T00:00:00ZTextJournal contributioninfo:eu-repo/semantics/publishedVersiontextcontribution to journal10.1109/access.2021.3072567https://figshare.com/articles/journal_contribution/Novel_Ternary_Adder_and_Multiplier_Designs_Without_Using_Decoders_or_Encoders/24042504CC BY 4.0info:eu-repo/semantics/openAccessoai:figshare.com:article/240425042021-04-12T00:00:00Z |
| spellingShingle | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders Jihad Mohamed Aljaam (16864257) Engineering Electronics, sensors and digital hardware Information and computing sciences Distributed computing and systems software Mathematical sciences Applied mathematics Transistors CNTFETs Logic gates Power supplies Threshold voltage Internet of Things Energy consumption Carbon nano-tube field effect transistors (CNTFET) Noise immunity curve (NIC) PVT variations Ternary logic circuits Unary operators |
| status_str | publishedVersion |
| title | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| title_full | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| title_fullStr | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| title_full_unstemmed | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| title_short | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| title_sort | Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders |
| topic | Engineering Electronics, sensors and digital hardware Information and computing sciences Distributed computing and systems software Mathematical sciences Applied mathematics Transistors CNTFETs Logic gates Power supplies Threshold voltage Internet of Things Energy consumption Carbon nano-tube field effect transistors (CNTFET) Noise immunity curve (NIC) PVT variations Ternary logic circuits Unary operators |