Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

<p>Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices...

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Bibliographic Details
Main Author: Jihad Mohamed Aljaam (16864257) (author)
Other Authors: Ramzi A. Jaber (16888755) (author), Somaya Ali Al-Maadeed (16864254) (author)
Published: 2021
Subjects:
Engineering
Electronics, sensors and digital hardware
Information and computing sciences
Distributed computing and systems software
Mathematical sciences
Applied mathematics
Transistors
CNTFETs
Logic gates
Power supplies
Threshold voltage
Internet of Things
Energy consumption
Carbon nano-tube field effect transistors (CNTFET)
Noise immunity curve (NIC)
PVT variations
Ternary logic circuits
Unary operators
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