A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization
<div><p>Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduce...
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2021
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| _version_ | 1864513506085175296 |
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| author | Muhammad Ali Akbar (16875915) |
| author2 | Bo Wang (86769) Amine Bermak (1895947) |
| author2_role | author author |
| author_facet | Muhammad Ali Akbar (16875915) Bo Wang (86769) Amine Bermak (1895947) |
| author_role | author |
| dc.creator.none.fl_str_mv | Muhammad Ali Akbar (16875915) Bo Wang (86769) Amine Bermak (1895947) |
| dc.date.none.fl_str_mv | 2021-07-26T03:00:00Z |
| dc.identifier.none.fl_str_mv | 10.3390/electronics10151791 |
| dc.relation.none.fl_str_mv | https://figshare.com/articles/journal_contribution/A_High-Speed_Parallel_Architecture_for_Ripple_Carry_Adder_with_Fault_Detection_and_Localization/26965090 |
| dc.rights.none.fl_str_mv | CC BY 4.0 info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Engineering Electronics, sensors and digital hardware fast adder hybrid adder ripple carry adder self-checking |
| dc.title.none.fl_str_mv | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| dc.type.none.fl_str_mv | Text Journal contribution info:eu-repo/semantics/publishedVersion text contribution to journal |
| description | <div><p>Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.</p><p> </p></div><h2>Other Information</h2> <p> Published in: Electronics<br> License: <a href="https://creativecommons.org/licenses/by/4.0/" target="_blank">https://creativecommons.org/licenses/by/4.0/</a><br>See article on publisher's website: <a href="https://dx.doi.org/10.3390/electronics10151791" target="_blank">https://dx.doi.org/10.3390/electronics10151791</a></p> |
| eu_rights_str_mv | openAccess |
| id | Manara2_e95023d6e84a9a85984e332e118ea7f5 |
| identifier_str_mv | 10.3390/electronics10151791 |
| network_acronym_str | Manara2 |
| network_name_str | Manara2 |
| oai_identifier_str | oai:figshare.com:article/26965090 |
| publishDate | 2021 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| rights_invalid_str_mv | CC BY 4.0 |
| spelling | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and LocalizationMuhammad Ali Akbar (16875915)Bo Wang (86769)Amine Bermak (1895947)EngineeringElectronics, sensors and digital hardwarefast adderhybrid adderripple carry adderself-checking<div><p>Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.</p><p> </p></div><h2>Other Information</h2> <p> Published in: Electronics<br> License: <a href="https://creativecommons.org/licenses/by/4.0/" target="_blank">https://creativecommons.org/licenses/by/4.0/</a><br>See article on publisher's website: <a href="https://dx.doi.org/10.3390/electronics10151791" target="_blank">https://dx.doi.org/10.3390/electronics10151791</a></p>2021-07-26T03:00:00ZTextJournal contributioninfo:eu-repo/semantics/publishedVersiontextcontribution to journal10.3390/electronics10151791https://figshare.com/articles/journal_contribution/A_High-Speed_Parallel_Architecture_for_Ripple_Carry_Adder_with_Fault_Detection_and_Localization/26965090CC BY 4.0info:eu-repo/semantics/openAccessoai:figshare.com:article/269650902021-07-26T03:00:00Z |
| spellingShingle | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization Muhammad Ali Akbar (16875915) Engineering Electronics, sensors and digital hardware fast adder hybrid adder ripple carry adder self-checking |
| status_str | publishedVersion |
| title | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_full | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_fullStr | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_full_unstemmed | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_short | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_sort | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| topic | Engineering Electronics, sensors and digital hardware fast adder hybrid adder ripple carry adder self-checking |