Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage.
<p>Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage.</p>
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2025
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| _version_ | 1852020382264983552 |
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| author | Ayesha Waris (21368446) |
| author2 | Arshad Aziz (3342512) Bilal Muhammad Khan (16050362) |
| author2_role | author author |
| author_facet | Ayesha Waris (21368446) Arshad Aziz (3342512) Bilal Muhammad Khan (16050362) |
| author_role | author |
| dc.creator.none.fl_str_mv | Ayesha Waris (21368446) Arshad Aziz (3342512) Bilal Muhammad Khan (16050362) |
| dc.date.none.fl_str_mv | 2025-05-15T15:41:49Z |
| dc.identifier.none.fl_str_mv | 10.1371/journal.pone.0323224.g012 |
| dc.relation.none.fl_str_mv | https://figshare.com/articles/figure/Coefficient_reordering_in_7_stages_of_MDC2NTT_a_First_stage_b_Second_stage_c_Seventh_stage_/29076946 |
| dc.rights.none.fl_str_mv | CC BY 4.0 info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Microbiology Biological Sciences not elsewhere classified Information Systems not elsewhere classified twiddle factor storage target fpga platform resource sharing technique propose various optimizations polynomial multiplication based path delay commutator number theoretic transform minimize resource consumption input output coefficients based modular multiplier based memory units xlink "> crystals kyber </ p xilinx artix using 29 time product rom memories resistant algorithm pwm operations presented architectures ntt ). national institute intt architecture comparable atp art architectures architectural level 7 xc7a100t |
| dc.title.none.fl_str_mv | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| dc.type.none.fl_str_mv | Image Figure info:eu-repo/semantics/publishedVersion image |
| description | <p>Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage.</p> |
| eu_rights_str_mv | openAccess |
| id | Manara_4ada403f239f623ec4fcd4e6fbbf0268 |
| identifier_str_mv | 10.1371/journal.pone.0323224.g012 |
| network_acronym_str | Manara |
| network_name_str | ManaraRepo |
| oai_identifier_str | oai:figshare.com:article/29076946 |
| publishDate | 2025 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| rights_invalid_str_mv | CC BY 4.0 |
| spelling | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage.Ayesha Waris (21368446)Arshad Aziz (3342512)Bilal Muhammad Khan (16050362)MicrobiologyBiological Sciences not elsewhere classifiedInformation Systems not elsewhere classifiedtwiddle factor storagetarget fpga platformresource sharing techniquepropose various optimizationspolynomial multiplication basedpath delay commutatornumber theoretic transformminimize resource consumptioninput output coefficientsbased modular multiplierbased memory unitsxlink "> crystalskyber </ pxilinx artixusing 29time productrom memoriesresistant algorithmpwm operationspresented architecturesntt ).national instituteintt architecturecomparable atpart architecturesarchitectural level7 xc7a100t<p>Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage.</p>2025-05-15T15:41:49ZImageFigureinfo:eu-repo/semantics/publishedVersionimage10.1371/journal.pone.0323224.g012https://figshare.com/articles/figure/Coefficient_reordering_in_7_stages_of_MDC2NTT_a_First_stage_b_Second_stage_c_Seventh_stage_/29076946CC BY 4.0info:eu-repo/semantics/openAccessoai:figshare.com:article/290769462025-05-15T15:41:49Z |
| spellingShingle | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. Ayesha Waris (21368446) Microbiology Biological Sciences not elsewhere classified Information Systems not elsewhere classified twiddle factor storage target fpga platform resource sharing technique propose various optimizations polynomial multiplication based path delay commutator number theoretic transform minimize resource consumption input output coefficients based modular multiplier based memory units xlink "> crystals kyber </ p xilinx artix using 29 time product rom memories resistant algorithm pwm operations presented architectures ntt ). national institute intt architecture comparable atp art architectures architectural level 7 xc7a100t |
| status_str | publishedVersion |
| title | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| title_full | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| title_fullStr | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| title_full_unstemmed | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| title_short | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| title_sort | Coefficient reordering in 7 stages of MDC2NTT (a) First stage (b) Second stage (c) Seventh stage. |
| topic | Microbiology Biological Sciences not elsewhere classified Information Systems not elsewhere classified twiddle factor storage target fpga platform resource sharing technique propose various optimizations polynomial multiplication based path delay commutator number theoretic transform minimize resource consumption input output coefficients based modular multiplier based memory units xlink "> crystals kyber </ p xilinx artix using 29 time product rom memories resistant algorithm pwm operations presented architectures ntt ). national institute intt architecture comparable atp art architectures architectural level 7 xc7a100t |