FPGA-based Parallel Hardware Architecture for Real-time Object Classification

FPGA-based Parallel Hardware Architecture for Real-time Object Classification

A Master of Science thesis in Computer Engineering by Murad Mohammad Qasaimeh entitled, "FPGA-based Parallel Hardware Architecture for Real-time Object Classification," submitted in June 2014. Thesis advisor is Dr. Tamer Shanableh and co-advisor is Dr. Assim Sagahyroon. Available are both...

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Bibliographic Details
Main Author: Qasaimeh, Murad Mohammad (author)
Format: doctoralThesis
Published: 2014
Subjects:
Field Programmable Gate Array (FPGA)
Scale Invariant Feature Transform (SIFT)
Support Vector Machine (SVM)
object recognition
object detection
Computer vision
Field programmable gate arrays
Pattern recognition systems
Image processing
Digital techniques
Online Access:http://hdl.handle.net/11073/7511
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Summary:A Master of Science thesis in Computer Engineering by Murad Mohammad Qasaimeh entitled, "FPGA-based Parallel Hardware Architecture for Real-time Object Classification," submitted in June 2014. Thesis advisor is Dr. Tamer Shanableh and co-advisor is Dr. Assim Sagahyroon. Available are both soft and hard copies of the thesis.

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