A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme حسب Fang Tang (116243)

"…Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). …"