A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder حسب Sait, Sadiq M.

"…The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modeled in AHPL to verify functional correctness. …"
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FoGMatch حسب Arisdakessian, Sarhad

"…Our solution consists of (1) two optimization problems, one for the IoT devices and one for the fog nodes, (2) preference functions for both the IoT and fog layers to help them rank each other on the basis of several criteria such latency and resource utilization, and (3) centralized and distributed intelligent scheduling algorithms that consider the preferences of both the fog and IoT layers to improve the performance of the overall IoT ecosystem. …"
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