Predictions from a Universal Value Function Approximator (UVFA) algorithm. by Sam Hall-McMaster (10343795)

“…Each panel includes three plots: the theoretical predictions of a UVFA algorithm, the theoretical predictions of an SF&GPI algorithm, and empirical choices from human participants. …”

Access control pseudo-code. by Yonggang Huang (223155)

Proportion of positive results in each algorithm and latent prevalences by year. by Jia Wei (120974)

Butterfly unit for CT/GS/MM operation. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

NTT operations in MDC2NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

TW management in MDC4NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

NTT/INTT/PWM operations in MDC4NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

Coefficient access scheme in MDC4NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

Read Write operations in memory-based FIFOs. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

PWM calculations broken into simpler operations. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

TW management in MDC2NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

INTT operations in MDC2NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

(a) CT (b) GS butterfly. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

Butterfly unit for CT/GS operation. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

PWM operations in MDC4NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

Barrett reduction unit. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

PWM operation in MDC2NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

Block diagram for MDC4NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

Timing diagram for PWM operation. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”

NTT/INTT/PWM operations in MDC2NIP. by Ayesha Waris (21368446)

“…The presented architectures are implemented on Xilinx Artix-7 XC7A100T-3 device using Vivado Design Suite 2022.2 and coded using Verilog HDL. …”