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level coding » level according (Expand Search), level modeling (Expand Search), level using (Expand Search)
implementing based » implementing system (Expand Search), implementing a (Expand Search), implementing targeted (Expand Search)
coding algorithm » cosine algorithm (Expand Search), modeling algorithm (Expand Search), finding algorithm (Expand Search)
data algorithm » data algorithms (Expand Search), update algorithm (Expand Search), atlas algorithm (Expand Search)
element data » settlement data (Expand Search), relevant data (Expand Search), movement data (Expand Search)
level coding » level according (Expand Search), level modeling (Expand Search), level using (Expand Search)
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Algorithm parameter settings employed in the experiments on simulated data.
Published 2024Subjects: -
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Practical implementation of an End-to-end methodology for SPC of 3-D part geometry: A case study
Published 2025“…<p>Del Castillo and Zhao have recently proposed a new methodology for the Statistical Process Control (SPC) of discrete parts whose 3-dimensional (3D) geometrical data are acquired with non-contact sensors. The approach is based on monitoring the spectrum of the Laplace–Beltrami (LB) operator of each scanned part estimated using finite element methods (FEM). …”
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Butterfly unit for CT/GS/MM operation.
Published 2025“…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
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97
NTT operations in MDC2NIP.
Published 2025“…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
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TW management in MDC4NIP.
Published 2025“…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
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NTT/INTT/PWM operations in MDC4NIP.
Published 2025“…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
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Coefficient access scheme in MDC4NIP.
Published 2025“…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”