Showing 81 - 100 results of 1,795 for search '(((( implementing based algorithm ) OR ( element data algorithm ))) OR ( level coding algorithm ))', query time: 0.43s Refine Results
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    Practical implementation of an End-to-end methodology for SPC of 3-D part geometry: A case study by Yulin An (833223)

    Published 2025
    “…<p>Del Castillo and Zhao have recently proposed a new methodology for the Statistical Process Control (SPC) of discrete parts whose 3-dimensional (3D) geometrical data are acquired with non-contact sensors. The approach is based on monitoring the spectrum of the Laplace–Beltrami (LB) operator of each scanned part estimated using finite element methods (FEM). …”
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    Butterfly unit for CT/GS/MM operation. by Ayesha Waris (21368446)

    Published 2025
    “…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
  17. 97

    NTT operations in MDC2NIP. by Ayesha Waris (21368446)

    Published 2025
    “…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
  18. 98

    TW management in MDC4NIP. by Ayesha Waris (21368446)

    Published 2025
    “…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
  19. 99

    NTT/INTT/PWM operations in MDC4NIP. by Ayesha Waris (21368446)

    Published 2025
    “…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”
  20. 100

    Coefficient access scheme in MDC4NIP. by Ayesha Waris (21368446)

    Published 2025
    “…Moreover, we propose various optimizations at architectural level to minimize resource consumption such as FIFO-based memory units for buffering of input output coefficients, LUT-based modular multiplier and distributed-ROM memories for twiddle factor storage. …”