Al-Suwaiyan, A. S. M., & unknown. (2002). Efficient test relaxation techniques for combinational logic circuits.
Chicago Style (17th ed.) CitationAl-Suwaiyan, Ali Saleh Mohammed, and unknown. Efficient Test Relaxation Techniques for Combinational Logic Circuits. 2002.
MLA (9th ed.) CitationAl-Suwaiyan, Ali Saleh Mohammed, and unknown. Efficient Test Relaxation Techniques for Combinational Logic Circuits. 2002.
Warning: These citations may not always be 100% accurate.