New fault models and efficient BIST algorithms for dual-portmemories
The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silic...
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| Other Authors: | , , , |
| Format: | article |
| Published: |
1997
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| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14841/1/14841_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14841/2/14841_2.doc |
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