Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan recon...
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14310/1/14310_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14310/2/14310_2.doc |
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