Efficient O(n) BIST algorithms for DDNPS faults in dual portmemories

Efficient O(n) BIST algorithms for DDNPS faults in dual portmemories

The testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(n) te...

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محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Amin, A.A. (author)
مؤلفون آخرون:	Osman, M.Y. (author), Abdel-Aal, R.E. (author), Al-Muhtaseb, Husni (author), unknown (author)
التنسيق:	article
منشور في:	2020
الموضوعات:	Computer
الوصول للمادة أونلاين:	https://eprints.kfupm.edu.sa/id/eprint/14149/1/14149_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14149/2/14149_2.doc
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