Efficient O(n) BIST algorithms for DDNPS faults in dual portmemories
The testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(n) te...
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| Other Authors: | , , , |
| Format: | article |
| Published: |
2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14149/1/14149_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14149/2/14149_2.doc |
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