On Test Vector Reordering for Combinational Circuits
The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such away that reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficie...
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| Format: | article |
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2004
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/164/1/On_Test_Vector_Reordering_for_Combinational_Circuits_ICM2004.pdf |
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