EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI
Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M<N. A major motivation for network folding is the severely limited number of I/O pins in microelectronic packages such as VLSI chips or multichip modu...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2020
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/293/1/J_AlNuweiri_VLSI_June1995.pdf |
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| _version_ | 1864513380280172544 |
|---|---|
| author | AL-Nuweir, H. M. |
| author2 | Sait, Sadiq M. unknown |
| author2_role | author author |
| author_facet | AL-Nuweir, H. M. Sait, Sadiq M. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | AL-Nuweir, H. M. Sait, Sadiq M. unknown |
| dc.date.*.fl_str_mv | 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/293/1/J_AlNuweiri_VLSI_June1995.pdf EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 3 (2): 254-263 JUN 1995. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/293/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M<N. A major motivation for network folding is the severely limited number of I/O pins in microelectronic packages such as VLSI chips or multichip module (MCM) packages. Cost overhead and performance degradationdue to off chip communication as well as long on chip wires may render implementing otherwise good designs infeasible or inefficient and systematic methodology is proposed for designing folded permutation networks that can be route the class of bit-permute-complement (BPC) permutations. In particulaer, is is shown that any folded BPC permutation network can be contructed using only two stages of uniform-size transpose networks. This results in highly modular structures for bpc networks. The methodology trades off speed (time), with I/O and chip area. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_4d9a0ba6b6c98e0029d7a5505acff88c |
| identifier_str_mv | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 3 (2): 254-263 JUN 1995. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::293 |
| publishDate | 2020 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSIAL-Nuweir, H. M.Sait, Sadiq M.unknownComputerNetwork folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M<N. A major motivation for network folding is the severely limited number of I/O pins in microelectronic packages such as VLSI chips or multichip module (MCM) packages. Cost overhead and performance degradationdue to off chip communication as well as long on chip wires may render implementing otherwise good designs infeasible or inefficient and systematic methodology is proposed for designing folded permutation networks that can be route the class of bit-permute-complement (BPC) permutations. In particulaer, is is shown that any folded BPC permutation network can be contructed using only two stages of uniform-size transpose networks. This results in highly modular structures for bpc networks. The methodology trades off speed (time), with I/O and chip area.ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/293/1/J_AlNuweiri_VLSI_June1995.pdf EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 3 (2): 254-263 JUN 1995. enhttps://eprints.kfupm.edu.sa/id/eprint/293/2020info:eu-repo/semantics/openAccessoai::2932019-11-01T13:23:31Z |
| spellingShingle | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI AL-Nuweir, H. M. Computer |
| status_str | publishedVersion |
| title | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| title_full | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| title_fullStr | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| title_full_unstemmed | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| title_short | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| title_sort | EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/293/1/J_AlNuweiri_VLSI_June1995.pdf |