EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI
Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M<N. A major motivation for network folding is the severely limited number of I/O pins in microelectronic packages such as VLSI chips or multichip modu...
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| Main Author: | AL-Nuweir, H. M. (author) |
|---|---|
| Other Authors: | Sait, Sadiq M. (author), unknown (author) |
| Format: | article |
| Published: |
2020
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| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/293/1/J_AlNuweiri_VLSI_June1995.pdf |
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