Formal synthesis of VLSI layouts from algorithmic specifications
Due to advances in VLSI technology, it is possible to implement complex digital systems on a single chip. However modeling such large and complex at structural level is tedious and error prone. This fact has motivated the development of several high-level synthesis systems. The process consists of t...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | , , |
| Format: | article |
| Published: |
2020
|
| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/367/1/VLSI_layouts.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|