Formal synthesis of VLSI layouts from algorithmic specifications
Due to advances in VLSI technology, it is possible to implement complex digital systems on a single chip. However modeling such large and complex at structural level is tedious and error prone. This fact has motivated the development of several high-level synthesis systems. The process consists of t...
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| Format: | article |
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2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/367/1/VLSI_layouts.pdf |
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| Summary: | Due to advances in VLSI technology, it is possible to implement complex digital systems on a single chip. However modeling such large and complex at structural level is tedious and error prone. This fact has motivated the development of several high-level synthesis systems. The process consists of translating the abstract behavioural representation. In this paper we present a formal approach for high level synthesis. This formal high level syntesis system uses recursive algorithms to model the behaviour to be synthesized. These algorithms can be mathematically verified for correctness before begin subjected to the task of translation. As a case study, the modelling and synthesis of VLSI layouts for matrix-matrix multipliers is discussed. Keywords: Formal synthesis, VLSI layous, Algorithmic specifications, high level synthesis |
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