Design of a programmable length FIFO memory and its controller.
This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length.
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1988
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