Design of a programmable length FIFO memory and its controller.
This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length.
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , , |
| التنسيق: | article |
| منشور في: |
1988
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| الموضوعات: | |
| الوسوم: |
إضافة وسم
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| _version_ | 1864513380796071936 |
|---|---|
| author | Kulaib, Munir A. |
| author2 | Beckhoff, Gerhard F. Sait, Sadiq M. unknown |
| author2_role | author author author |
| author_facet | Kulaib, Munir A. Beckhoff, Gerhard F. Sait, Sadiq M. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Kulaib, Munir A. Beckhoff, Gerhard F. Sait, Sadiq M. unknown |
| dc.date.none.fl_str_mv | 1988-11-05 2020 |
| dc.identifier.none.fl_str_mv | (1988) Design of a programmable length FIFO memory and its controller. International Journal of Electronics, 65 (5). pp. 923-932. 10.1080/00207218808945291 |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/1267/ 10.1080/00207218808945291 |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Electrical |
| dc.title.none.fl_str_mv | Design of a programmable length FIFO memory and its controller. |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_7a426f7a82f64a2bff4fec71c9535049 |
| identifier_str_mv | (1988) Design of a programmable length FIFO memory and its controller. International Journal of Electronics, 65 (5). pp. 923-932. 10.1080/00207218808945291 |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::1267 |
| publishDate | 1988 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Design of a programmable length FIFO memory and its controller.Kulaib, Munir A.Beckhoff, Gerhard F.Sait, Sadiq M.unknownElectricalThis paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length.1988-11-052020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article (1988) Design of a programmable length FIFO memory and its controller. International Journal of Electronics, 65 (5). pp. 923-932. 10.1080/00207218808945291https://eprints.kfupm.edu.sa/id/eprint/1267/10.1080/00207218808945291info:eu-repo/semantics/openAccessoai::12672019-11-01T13:26:33Z |
| spellingShingle | Design of a programmable length FIFO memory and its controller. Kulaib, Munir A. Electrical |
| status_str | publishedVersion |
| title | Design of a programmable length FIFO memory and its controller. |
| title_full | Design of a programmable length FIFO memory and its controller. |
| title_fullStr | Design of a programmable length FIFO memory and its controller. |
| title_full_unstemmed | Design of a programmable length FIFO memory and its controller. |
| title_short | Design of a programmable length FIFO memory and its controller. |
| title_sort | Design of a programmable length FIFO memory and its controller. |
| topic | Electrical |