Back-end design of a formal high level synthesis system
A complete design and implementation of a cell library has been accomplished in this work. This cell library supports a formal high level synthesis framework. The library contains the logic level models of all primitive functions of a Realization Specification Language (RSL). Modular design methodol...
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| Format: | masterThesis |
| Published: |
1993
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/19/1/1354058.pdf |
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| Summary: | A complete design and implementation of a cell library has been accomplished in this work. This cell library supports a formal high level synthesis framework. The library contains the logic level models of all primitive functions of a Realization Specification Language (RSL). Modular design methodology is employed to support the expandability of basic cells. Examples of a formal adder, multiplier, inner-product and matrix-matrix multiplier are presented. Advisor: Prof. Sadiq M. Sait, Co-Advisors: Dr. Khalid M. Elleithy and Dr. Samir Abdul Jauwad. |
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