An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology
A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achie...
Saved in:
| Main Author: | Bouhraoua, A. (author) |
|---|---|
| Other Authors: | Elrabaa, M. (author), unknown (author) |
| Format: | article |
| Published: |
2006
|
| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14087/1/14087_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14087/2/14087_2.doc |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine
by: Bouhraoua, A.
Published: (2006) -
A Portable Clock Recovery Circuit (CRC) For Systems-On-Chip Serial Data Communication
by: Elrabaa, Muhammad
Published: (2006) -
A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links
by: Elrabaa, Muhammad
Published: (2006) -
Speed optimised array architecture for flash EEPROMs
by: Amin, A.A.M.
Published: (1993) -
Efficient Approach for Processing of Hexagonally Sampled Exploration Seismic Data using Spiral Architecture.
by: unknown
Published: (2020)