Design, selection and implementation of flash erase EEPROM memorycells
The author reports an investigation into the design and process constraints of flash EEPROM memory cells. He describes several possible structures which were developed by the MOS memory RD group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested...
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| Format: | article |
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1992
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14481/1/14481_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14481/2/14481_2.doc |
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