Built-in self test logic for a histogrammer memory chip

مواد مشابهة

• A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures
  حسب: El-Maleh, Aiman H.
  منشور في: (2001)
• A hybrid test compression technique for efficient testing of systems-on-a-chip
  حسب: El-Maleh, A.H.
  منشور في: (2003)
• A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip
  حسب: El-Maleh, Aiman H.
  منشور في: (2003)
• Designing a self-timed arithmetic logic unit
  حسب: Maadi, Feras Ali Mohammed
  منشور في: (2004)
• A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
  حسب: El-Maleh, Aiman H.
  منشور في: (2001)