A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links
A new all-digital circuit scheme for clock and data re-timing functions for on-chip high-speed source synchronous data communications, such as in burst-mode data transmission over a network-on-chip is introduced. The new technique is non-PLL-based and is capable of retiming the output clock with the...
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| Format: | article |
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2006
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14026/1/14026_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14026/2/14026_2.doc |
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