An efficient test relaxation technique for combinational & full-scan sequential circuits
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper...
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| Format: | article |
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2002
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14181/1/14181_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14181/2/14181_2.doc |
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