An efficient test relaxation technique for combinational & full-scan sequential circuits

An efficient test relaxation technique for combinational & full-scan sequential circuits

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper...

وصف كامل

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	El-Maleh, A. (author)
مؤلفون آخرون:	Al-Suwaiyan, A. (author), unknown (author)
التنسيق:	article
منشور في:	2002
الموضوعات:	Computer
الوصول للمادة أونلاين:	https://eprints.kfupm.edu.sa/id/eprint/14181/1/14181_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14181/2/14181_2.doc
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

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