On test vector reordering for combinational circuits
The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such a way that it reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an eff...
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| Format: | article |
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2004
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14466/1/14466_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14466/2/14466_2.doc |
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