Speed optimised array architecture for flash EEPROMs
The author describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the...
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| Format: | article |
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1993
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14216/1/14216_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14216/2/14216_2.doc |
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