Speed optimised array architecture for flash EEPROMs
The author describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the...
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| Format: | article |
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1993
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14216/1/14216_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14216/2/14216_2.doc |
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| _version_ | 1864513402763739136 |
|---|---|
| author | Amin, A.A.M. |
| author2 | unknown |
| author2_role | author |
| author_facet | Amin, A.A.M. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Amin, A.A.M. unknown |
| dc.date.none.fl_str_mv | 1993-06 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14216/1/14216_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14216/2/14216_2.doc (1993) Speed optimised array architecture for flash EEPROMs. Circuits, Devices and Systems, IEE Proceedings G, 140. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14216/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Petroleum |
| dc.title.none.fl_str_mv | Speed optimised array architecture for flash EEPROMs |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | The author describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_ccbb9b3e82b597b4e34fb14c51dfb16d |
| identifier_str_mv | (1993) Speed optimised array architecture for flash EEPROMs. Circuits, Devices and Systems, IEE Proceedings G, 140. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14216 |
| publishDate | 1993 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Speed optimised array architecture for flash EEPROMsAmin, A.A.M.unknownPetroleumThe author describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cellsIEEE1993-062020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14216/1/14216_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14216/2/14216_2.doc (1993) Speed optimised array architecture for flash EEPROMs. Circuits, Devices and Systems, IEE Proceedings G, 140. enenhttps://eprints.kfupm.edu.sa/id/eprint/14216/info:eu-repo/semantics/openAccessoai::142162019-11-01T14:04:45Z |
| spellingShingle | Speed optimised array architecture for flash EEPROMs Amin, A.A.M. Petroleum |
| status_str | publishedVersion |
| title | Speed optimised array architecture for flash EEPROMs |
| title_full | Speed optimised array architecture for flash EEPROMs |
| title_fullStr | Speed optimised array architecture for flash EEPROMs |
| title_full_unstemmed | Speed optimised array architecture for flash EEPROMs |
| title_short | Speed optimised array architecture for flash EEPROMs |
| title_sort | Speed optimised array architecture for flash EEPROMs |
| topic | Petroleum |
| url | https://eprints.kfupm.edu.sa/id/eprint/14216/1/14216_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14216/2/14216_2.doc |