Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits
Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in o...
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2003
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/165/1/Test_Vector_Decomposition_Based_Static_Compaction_Algorithms_for_Combinational_Circuits_acm2003.pdf |
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