A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder
A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived...
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| Other Authors: | , , |
| Format: | article |
| Published: |
1989
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14067/1/14067_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14067/2/14067_2.doc |
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