A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder
A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| مؤلفون آخرون: | , , |
| التنسيق: | article |
| منشور في: |
1989
|
| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/14067/1/14067_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14067/2/14067_2.doc |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
| _version_ | 1864513402705018880 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | Damati, A.F. Rahman, M. unknown |
| author2_role | author author author |
| author_facet | Sait, Sadiq M. Damati, A.F. Rahman, M. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. Damati, A.F. Rahman, M. unknown |
| dc.date.none.fl_str_mv | 1989-04 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14067/1/14067_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14067/2/14067_2.doc (1989) A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder. Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean, 1. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14067/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modeled in AHPL to verify functional correctness. Implementation details are discussed. It is found that the proposed systolic design compares favorably with previous implementations of Viterbi decoders in terms of speed and modularity |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_de223e500d71e13c51a250405d3e39df |
| identifier_str_mv | (1989) A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder. Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean, 1. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14067 |
| publishDate | 1989 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoderSait, Sadiq M.Damati, A.F.Rahman, M.unknownComputerA novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modeled in AHPL to verify functional correctness. Implementation details are discussed. It is found that the proposed systolic design compares favorably with previous implementations of Viterbi decoders in terms of speed and modularityIEEE1989-042020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14067/1/14067_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14067/2/14067_2.doc (1989) A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder. Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean, 1. enenhttps://eprints.kfupm.edu.sa/id/eprint/14067/info:eu-repo/semantics/openAccessoai::140672019-11-01T14:04:00Z |
| spellingShingle | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder Sait, Sadiq M. Computer |
| status_str | publishedVersion |
| title | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| title_full | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| title_fullStr | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| title_full_unstemmed | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| title_short | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| title_sort | A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14067/1/14067_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14067/2/14067_2.doc |