Interconnect-Efficient LDPC Code Design
In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance....
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| Other Authors: | , , |
| Format: | article |
| Published: |
2006
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| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/162/1/Interconnect-Efficient_LDPC_Code_Design_ICM2006.pdf |
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