A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures
Recently, a new Built-In Self Test (BIST) methodology based on balanced bistable sequential kernels has been proposed that reduces the area overhead and performance degradation associated with the conventional BILBO-oriented BIST methodology. This new methodology guarantees high fault coverage but r...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2001
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/138/1/A_Retiming-Based_Test_Pattern_Generator_Design_for_Built-In_Self_Test_iscas2001.pdf |
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| _version_ | 1864513399770054656 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Osais, Yahya E. unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman H. Osais, Yahya E. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Osais, Yahya E. unknown |
| dc.date.none.fl_str_mv | 2001 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/138/1/A_Retiming-Based_Test_Pattern_Generator_Design_for_Built-In_Self_Test_iscas2001.pdf (2001) A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures. Int. Symp. on Circuits and Systems. pp. 550-553. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/138/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Recently, a new Built-In Self Test (BIST) methodology based on balanced bistable sequential kernels has been proposed that reduces the area overhead and performance degradation associated with the conventional BILBO-oriented BIST methodology. This new methodology guarantees high fault coverage but requires special test sequences and test pattern generator (TPG) designs. In this paper, we demonstrate the use of the retiming technique in designing TPGs for balanced bistable sequential kernels. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the designed TPGs in achieving higher fault coverage than the conventional maximal-length LFSR TPGs. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_f44b690e41703e4d31355f0a36d32aba |
| identifier_str_mv | (2001) A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures. Int. Symp. on Circuits and Systems. pp. 550-553. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::138 |
| publishDate | 2001 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path ArchitecturesEl-Maleh, Aiman H.Osais, Yahya E.unknownComputerRecently, a new Built-In Self Test (BIST) methodology based on balanced bistable sequential kernels has been proposed that reduces the area overhead and performance degradation associated with the conventional BILBO-oriented BIST methodology. This new methodology guarantees high fault coverage but requires special test sequences and test pattern generator (TPG) designs. In this paper, we demonstrate the use of the retiming technique in designing TPGs for balanced bistable sequential kernels. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the designed TPGs in achieving higher fault coverage than the conventional maximal-length LFSR TPGs.20012020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/138/1/A_Retiming-Based_Test_Pattern_Generator_Design_for_Built-In_Self_Test_iscas2001.pdf (2001) A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures. Int. Symp. on Circuits and Systems. pp. 550-553. enhttps://eprints.kfupm.edu.sa/id/eprint/138/info:eu-repo/semantics/openAccessoai::1382019-11-01T13:22:32Z |
| spellingShingle | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures El-Maleh, Aiman H. Computer |
| status_str | publishedVersion |
| title | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| title_full | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| title_fullStr | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| title_full_unstemmed | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| title_short | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| title_sort | A Retiming-Based Test Pattern Generator Design for Built-In Self Test of Data Path Architectures |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/138/1/A_Retiming-Based_Test_Pattern_Generator_Design_for_Built-In_Self_Test_iscas2001.pdf |