An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper,...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2002
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/141/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_and_Full-Scan_Sequential_Circuits_VTS2002.pdf |
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| _version_ | 1864513399772151808 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Al-Suwaiyan, Ali unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman H. Al-Suwaiyan, Ali unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Al-Suwaiyan, Ali unknown |
| dc.date.none.fl_str_mv | 2002 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/141/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_and_Full-Scan_Sequential_Circuits_VTS2002.pdf (2002) An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 20’th IEEE VLSI Test Symposium. pp. 53-59. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/141/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_f73f025680034270e4c82f0e42d0f121 |
| identifier_str_mv | (2002) An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 20’th IEEE VLSI Test Symposium. pp. 53-59. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::141 |
| publishDate | 2002 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential CircuitsEl-Maleh, Aiman H.Al-Suwaiyan, AliunknownComputerReducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.20022020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/141/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_and_Full-Scan_Sequential_Circuits_VTS2002.pdf (2002) An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 20’th IEEE VLSI Test Symposium. pp. 53-59. enhttps://eprints.kfupm.edu.sa/id/eprint/141/info:eu-repo/semantics/openAccessoai::1412019-11-01T13:22:33Z |
| spellingShingle | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits El-Maleh, Aiman H. Computer |
| status_str | publishedVersion |
| title | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| title_full | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| title_fullStr | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| title_full_unstemmed | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| title_short | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| title_sort | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/141/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_and_Full-Scan_Sequential_Circuits_VTS2002.pdf |