AN ON CHIP ALL-DIGITAL CONFIGURABLE CLOCK GENERATOR FOR ASICS' AT-SPEED TESTING
Saved in:
| Main Author: | unknown (author) |
|---|---|
| Format: | masterThesis |
| Published: |
2020
|
| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/138860/1/Mohammed_Al-Asali_Master_Thesis.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications
by: Elrabaa, M.E.S.
Published: (2006) -
An optimal formulation for test scheduling network-on-chip using multiple clock rates
by: Harmanani, Haidar M.
Published: (2017) -
A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links
by: Elrabaa, Muhammad
Published: (2006) -
Thermal-aware test scheduling using network-on-chip under multiple clock rates
by: Harmanani, Haidar M.
Published: (2013) -
An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates
by: Harmanani, Haidar
Published: (2017)