Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC
System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the case of non-mergeable legacy cores that have been placed and routed. This paper presents an efficient appr...
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| Format: | conferenceObject |
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2017
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| Online Access: | http://hdl.handle.net/10725/5458 http://dx.doi.org/10.1109/MWSCAS.2007.4488807 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4488807/ |
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